Fault Insertion Switch Architectures
Fault Insertion (FI) techniques are commonly used in applications where a controller is required to act responsibly when a fault on one of its inputs or outputs is present. The fault could be caused by faulty sensors, sensors which correctly report a fault or cable wiring problems. Cable wiring problems typically include open circuits, short circuits to other wires and in some cases leakage paths caused by contamination such as oil spillage or water ingress.
Various architectures for switching systems have been deployed to simulate the most common types of fault that a controller
can encounter, having a programmable way of introducing these faults allows users to run standardized tests on controllers
that can be performed during acceptance testing of a new design or when the design is upgraded to include new features
(software or hardware).
The principal of fault insertion is simple, the system intercepts wires between the sensors (or actuators) and the controllers and either passes the signal through unchanged or adds a fault condition. As always, the more capable the fault insertion system is the more expensive and larger the system becomes. Higher current or voltage ratings ratings make the relays larger and the modules less dense.
On this page we show some of the common fault insertion architectures used based on examples from Pickering Interfaces fault insertion modules.
Single Fault Bus Architecture
This architecture is used on our 40-195 and the 40-196 fault insertion modules, in these two cases the input connections are grouped in pairs and then multiple pairs have a connection allowed to a single fault bus. Using this architecture a variety of faults can be simulated:
- Either input connection disconnected from its output
- Input connection pair shorted together
- Either input connected to the fault bus
The fault bus could be a powers supply, system ground or some other connect in the system. If more than one fault bus condition is required to be simulated then additional (external) switching has to be used to expand the possibilities, or a different architecture used.
Dual Fault Bus Architecture
This architecture is used in a variety of fault insertion modules and provides more flexibility, examples include 40-190, 40-191, 40-192, 40-193, 40-194.
Using this architecture a variety of faults can be simulated:
- Any input disconnected from its output
- Any output connected to one of two fault buses
- Any output shorted to any other output if the fault bus is disconnected.
Fault Insertion Matrix
The 40-592A and 40-595A fault insertion switch modules provide a more complex architecture that can be used in a variety of ways for complex tests.
The common way of using the fault matrix is for the connection between the controller and the sensor to be on the X axis. A connection from an input (for example) is made to Breakout X1.1 and its output is from Breakout X1.2. In this example the default condition is for a connection to be made by the normally closed relay.
Much more complex faults can be introduced:
- Open circuit between input and output
- Fault on the output to X1.2, which could be component inserted by a patch panel arrangement.
- Connection of any input to one of four fault buses (Y1 to Y4)
- Connection of any output to one of of four fault buses (Y5 to Y8)
- Short circuits between wires by using an unused X column to provide the short on an unused Y row
- Addition of other shunt components between wires using Y axis.
The variety of fault types that be simulated is large, and the third connection on each X axis adds a great deal more flexibility. There is of course a cost to this, this approach is more complex and costly and is more likely to be used in aviation applications than automotive for that reason.
Examples of how to use the 40-592A and 40-95A can be found here Fault Insertion with 40-592A and 40-595A.
The solution can also be used as a conventional matrix or as a dual matrix, though in the latter case some care needs to be taken about the start up condition since the initialized state is a single matrix.