Understanding the BRIC Large PXI Matrix

    There is a demand for matrices in PXI based test systems where the matrix does not fit in a single slot module. Matrices can be expanded to make up larger configurations but the methods used are time consuming for the user to configure, often have performance implications and add costs. To address these applications Pickering Interfaces created the BRIC family of matrices.

    Since the original introduction of the BRIC in 2002, a new family of compatible BRIC's was introduced in 2009 which includes the embedded Built-in Relay Self-Test (BIRST).

    BRIC Overview

    BRIC's use a set of matrix daughter cards connected to a backplane 

    BRIC's use a set of matrix daughter cards connected to a backplane,
    some configurations are connected via isolation relays to increase matrix BW

    The BRIC is a high-density switching matrix that can occupy 2, 4 or 8 PXI slots. The BRIC uses a modular construction to allow various matrix sizes to be built up, providing an elegant way for Pickering Interfaces to create matrices with varying X and Y dimensions from a set of PCB assemblies. 

    The core of the BRIC is a backplane which has a set of daughter cards that can plugged into it, the backplane and the daughter cards being mounted in a metal enclosure that provides mechanical strength and rigidity. The backplane is not to be confused with the PXI backplane—the BRIC only has one connector that connects to the PXI backplane. The BRIC backplane runs parallel to the PXI backplane but is physically separated from it. 

    The BRIC contains a primary daughter card (Daughter Card 1) that provides connections to both the Y axis and the X axis of the matrix. This card is connected to the BRIC backplane that provides analog bus interconnections to other daughter cards. The BRIC backplane then has further daughter cards added to it that expand the X axis of the matrix. 

    Connections are brought to the front panel on a connector, typically a Micro D Type, D Type or 160 pin DIN41612. 

    The primary daughter card determines the dimension of the Y axis and the daughter cards simply expand the number of X axis points. Each daughter card must have the same Y axis dimension as the primary daughter card and a selection of different daughter cards are available to fit the various versions of the BRIC. The BRIC is available in standard Y axis sizes of 4, 8 and 16, other sizes can be offered by reducing the number of relays loaded on to the cards. In addition to 1 pole switches, screened and 2 pole versions of the matrix can be provided. 

    To maximize the bandwidth of the analog interconnection systems the daughter cards can include isolation switches which can be used to isolate the Y axis of any connection into the daughter card. If none of the switches on a particular Y axis line of the daughter card are closed then the isolation switch disconnects that line from the matrix, reducing the load on the line and maximizing the switch bandwidth

    . Front view of BRIC showing user connectors  

    Front view of BRIC showing user connectors. X and Y axis connections are 
    brought out on the left hand connector, X connections only on the remaining connectors 

    Rear view of a BRIC module, the connector on the right is the connector that plugs into the PXI backplane 

    Rear view of a BRIC module, the connector on the right is the connector that plugs into the PXI backplane 

    The Relays

    The BRIC is available in designs that use reed relays, EMR's or solid state relays.

    The reed relays were created with the assistance of Pickering Interfaces sister company Pickering Electronics and were designed specifically for BRIC's to minimize the footprint on the daughter cards and therefore maximize the number of relays that can be fitted.

    EMR versions use a compact 4th Generation Telecomm relay that has been extensively evaluated for use in Pickering Interfaces switching systems.

    Why use the BRIC?

    The BRIC offers the test system designer a number of key advantages over the use of individual switching cards

    • Robustness in the face of changing requirements. If the test requirements change then, provided the Y dimension of the matrix can support the number of simultaneous connections required, the BRIC can be upgraded.
    • Better re-use of designs. The cost of designing tests systems can often be higher than the hardware costs.Using the BRIC approach minimises the test system investment and makes it more likely the same setup can be used for other test systems.
    • Better re-use of modules. Once the requirements for a particular part have been met in manufacturing or engineering the module can be transferred to another system with much better chances of meeting the test requirements.
    • Less volume in the PXI chassis. Thanks to the use of high density modular switching the overall number of slots occupied by the switching system can be less than taking an individual approach to each switching requirement.
    • Lower hardware costs. The BRIC module will often cost less than buying separate PXI modules because the PXI overhead is reduced and the number of separate PCBs is reduced. Those that are used are functionally similar or identical, reducing the module design and manufacturing cost.
    • Lower integration costs. The designer does not have to spend time selecting which modules he needs, learning how to drive different switch modules or having to take into account the interconnectivity limitations of his switching system. With the BRIC many more things are possible.
    • Fast operating times and long operational life through the use of high quality relays.
    • Higher relay densities than that achieved in competitive solutions resulting in smaller test system size and higher operating bandwidth.

    Clearly there are switching applications for which the BRIC is not suited, some applications for example may be better served by LXI based matrix solutions using Ethernet control. However, the BRIC provides a valuable solution for the testing of devices with a matrix where there are a high number input and output access points required with up to 35 MHz bandwidth.

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